1. Field of the Invention
One disclosed aspect of the embodiments relates to a technique for adjusting phases between clocks in a semiconductor integrated circuit.
2. Description of the Related Art
Semiconductor integrated circuits are used in information processing apparatuses such as personal computers (PCs) and image forming apparatuses such as multi function printers (MFPs). Generally, a semiconductor integrated circuit used for these apparatuses incorporates a bus structure to perform data transfer to/from a central processing unit (CPU) and various peripheral functional circuits. In a bus in such a semiconductor integrated circuit, a flip-flop (FF) synchronization circuit operating on a clock-synchronous basis transmits and receives data. Data transfer by using a synchronous bus is achieved in this way. In synchronization circuit design, circuit design is performed on the premise of matched edge positions of clocks to achieve timing design in which the setup time and holding time of the FF are verified to ensure operations. Further, in a semiconductor integrated circuit using a plurality of clocks, if the relation between clocks for operating the FF is such that the ratio of respective clock frequencies is a natural number and edge positions are matched (hereinafter referred to as a synchronous relation), a normal operation as a synchronization circuit is ensured as long as timing design is satisfied with the clock cycle at higher speed. On the other hand, if the clocks for operating the FF are not in the above-described synchronous relation (in an asynchronous relation), the data transfer time is extremely short and accordingly the setup time and hold time of the FF cannot be satisfied. In this case, normal data transfer cannot be achieved. Therefore, in case of clocks in an asynchronous relation, normal data transfer is generally achieved by providing a synchronization circuit such as a double latch.
However, a configuration for performing data transfer using a synchronization circuit requires a larger number of clock cycles to perform data transfer than a configuration for performing data transfer without using a synchronization circuit. Therefore, the delay time until data transfer is completed increases to cause performance degradation of an apparatus using such a semiconductor integrated circuit.
A technique for preventing a delay time in data transfer by using a synchronization circuit is discussed, for example, in Japanese Patent Application Laid-Open No. 2012-99921. In data transfer between clocks in an asynchronous relation, the technique discussed in Japanese Patent Application Laid-Open No. 2012-99921 uses an enable signal indicating edge positions between clocks to achieve safe data transfer between clocks in an asynchronous relation without using a synchronization circuit.
In the technique discussed in Japanese Patent Application Laid-Open No. 2012-99921, since there needs to exist a timing at which edge positions of clocks are matched, data transfer between clocks in a completely asynchronous relation is to be necessarily abandoned. Further, in the case of a synchronization circuit using both a fixed-frequency clock and a variable-frequency clock, the synchronous relation between clocks is not uniquely determined. However, as described above, a configuration on the premise of the use of a synchronization circuit increases a delay time in data transfer, causing performance degradation of a semiconductor integrated circuit and an apparatus having the semiconductor integrated circuit.